The present invention relates to interconnect sutures and fabrication methods for integrated circuit memory.
A dynamic random access memory (DRAM) is a MOS memory device which stores a bit of information as a charge on a capacitor. Since this charge decays away in a finite length of time (usually in milliseconds), the DRAM cell periodically needs to be refreshed to restore the charge so that the DRAM retains its xe2x80x9cmemoryxe2x80x9d. There are many advantages of DRAMs, one of which is that the basic memory cell is small and, thus, a very dense array can be made using these cells. Therefore, DRAMs have a lower cost per bit than memories with less compact arrays. DRAMs are also fast for a system to access, giving them a high performance rating.
The basic memory cell of a DRAM consists of a single transistor and a capacitor. In a typical DRAM structure, the bottom storage electrode (composed e.g. of a noble metal such as plum, or a conductive oxide such as ruthenium oxide) is overlaid by a dielectric layer that has a high dielectric constant. A top electrode, which can be of the same material as the bottom storage electrode, can then be deposited over the resulting stacked cell capacitor structures. A polysilicon plug beneath the bottom electrode provides contact with an underlying transistor.
One type of DRAM cell is the capacitor-over-bitline (or xe2x80x9cCOBxe2x80x9d) cell, in which the storage capacitors are above the bitlines. This has the advantage that the whole area of the cell can be used for storage capacitors. It also has the advantage that exotic materials used for the capacitor plates and dielectric are far removed from the substrate, and used only at a very late stage of processing.
However, COB cells are not easy to fabricate. In particular, the vertical connections to the storage capacitor must extend up through the layer of bitlines without making contact to any of them. The resistance of the bitlines and the vertical connections should both be as low as possible (to avoid degrading speed), so it is desirable not to waste any space at the bitline level.
Bitline Self-Alignment to Vertical Connection
The present application discloses a new way to combine the metal bitline with the vertical interconnection to the capacitor over the bitline. In one class of embodiments, the vertical interconnect pillar is formed before fabrication of the bitline is completed. To accomplish this, the bitline metal is patterned using a step which allows it to extend vertically along the walls of the vertical interconnect pillar, but does not create any electrical connection between the bitline metal and the vertical interconnect pillar.
In another class of embodiments, a sacrificial layer is used to define the lateral layers of bitline
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following: simplicity of fabrication, without the contact filling steps normally required for COB structures.